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Verilog::Netlist::Port - Port for a Verilog Module

• NAME
• SYNOPSIS
• DESCRIPTION
• ACCESSORS
• MEMBER FUNCTIONS
• SEE ALSO
• AUTHORS

NAME

Verilog::Netlist::Port - Port for a Verilog Module

SYNOPSIS

  use Verilog::Netlist;

  ...
  my $port = $module->find_port ('pinname');
  print $port->name;

DESCRIPTION

Verilog::Netlist creates a port for every connection to the outside world in the current module.

ACCESSORS

See also Verilog::Netlist::Subclass for additional accessors and methods.

$self->array

Any array declaration for the port.

$self->comment

Any comment the user placed on the same line as the port.

$self->direction

The direction of the port: ``in'', ``out'', or ``inout''.

$self->module

Reference to the Verilog::Netlist::Module the port is in.

$self->name

The name of the port.

$self->net

Reference to the Verilog::Netlist::Net the port connects to. Only valid after the netlist is linked.

$self->type

The C++ type of the port.

MEMBER FUNCTIONS

See also Verilog::Netlist::Subclass for additional accessors and methods.

$self->dump

Prints debugging information for this port.

SEE ALSO

the Verilog::Netlist::Subclass manpage the Verilog::Netlist manpage

AUTHORS

Wilson Snyder <wsnyder@wsnyder.org>

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