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Verilog::Netlist::Net - Net for a Verilog Module

• NAME
• SYNOPSIS
• DESCRIPTION
• ACCESSORS
• MEMBER FUNCTIONS
• SEE ALSO
• AUTHORS

NAME

Verilog::Netlist::Net - Net for a Verilog Module

SYNOPSIS

  use Verilog::Netlist;

  ...
  my $net = $module->find_net ('signalname');
  print $net->name;

DESCRIPTION

Verilog::Netlist creates a net for every sc_signal declaration in the current module.

ACCESSORS

See also Verilog::Netlist::Subclass for additional accessors and methods.

$self->array

Any array (vector) declaration for the net. This is for multidimensional signals, for the width of a signal, use msb/lsb/width.

$self->comment

Any comment the user placed on the same line as the net.

$self->module

Reference to the Verilog::Netlist::Module the net is in.

$self->lsb

The least significant bit number of the net.

$self->msb

The most significant bit number of the net.

$self->name

The name of the net.

$self->type

The C++ type of the net.

$self->width

The width of the net in bits.

MEMBER FUNCTIONS

See also Verilog::Netlist::Subclass for additional accessors and methods.

$self->lint

Checks the net for errors. Normally called by Verilog::Netlist::lint.

$self->dump

Prints debugging information for this net.

$self->dump_drivers

Prints debugging information for this net, and all pins driving the net.

SEE ALSO

the Verilog::Netlist::Subclass manpage the Verilog::Netlist manpage

AUTHORS

Wilson Snyder <wsnyder@wsnyder.org>

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