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SystemC::Netlist - SystemC Netlist

• NAME
• SYNOPSIS
• DESCRIPTION
• FUNCTIONS
• SEE ALSO
• DISTRIBUTION
• AUTHORS

NAME

SystemC::Netlist - SystemC Netlist

SYNOPSIS

  use SystemC::Netlist;

  # See Verilog::Netlist for base functions

    $nl->autos();
    $nl->exit_if_error();

DESCRIPTION

SystemC::Netlist contains interconnect information about a whole design database. The classes of SystemC::Netlist parallel those of Verilog::Netlist, which should be seen for all documentation.

The database is composed of files, which contain the text read from each file.

A file may contain modules, which are individual blocks that can be instantiated (designs, in Synopsys terminology.)

Modules have ports, which are the interconnection between nets in that module and the outside world. Modules also have nets, (aka signals), which interconnect the logic inside that module.

Modules can also instantiate other modules. The instantiation of a module is a Cell. Cells have pins that interconnect the referenced module's pin to a net in the module doing the instantiation.

Each of these types, files, modules, ports, nets, cells and pins have a class. For example SystemC::Netlist::Cell has the list of SystemC::Netlist::Pin (s) that interconnect that cell.

FUNCTIONS

See Verilog::Netlist for all common functions.

$netlist->autos

Updates /*AUTO*/ comments in the internal database. Normally called before lint.

$netlist->sc_version

Return the version number of SystemC.

SEE ALSO

the SystemC::Netlist::Cell manpage, the SystemC::Netlist::File manpage, the SystemC::Netlist::Module manpage, the SystemC::Netlist::Net manpage, the SystemC::Netlist::Pin manpage, the SystemC::Netlist::Port manpage, the Verilog::Netlist::Subclass manpage

DISTRIBUTION

The latest version is available from CPAN and from http://veripool.com/.

AUTHORS

Wilson Snyder <wsnyder@wsnyder.org>

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